Background information respecting the 80386, its characteristics and its use in microcomputer systems including cache memory subsystems are described in Intel's "Introduction to the 80386", April 1986 and the 80386 Hardware Reference Manual (1986). The characteristics and operating performance of the 82385 are described in the Intel publication "82385 High Performance 32-Bit Cache Controller" (1987).
Devices for distributing a resource among a plurality of potential users are described in the above-identified applications, the disclosures of which are incorporated herein by reference. These applications describe distribution of a resource such as a computer bus subsystem and/or access to memory, among a plurality of devices on a single bus microcomputer system. Distribution of such a resource is commonly referred to as arbitration. The arbitration arrangements described in the above-referenced applications use distributed arbitration with a central supervisor to allocate the common resource to one of a plurality of potential users. However, the supervisor is controlled by the CPU so that, in the event the CPU requires access, it can control the supervisor in order to ensure that the CPU itself receives access to the common resource as required.
Microcomputer systems including a cache subsystem are, architecturally, significantly different from microcomputer systems without cache subsystems. Microcomputer systems with a cache subsystem operate as dual bus devices. More particularly, in microcomputer systems with a cache subsystem, there is a first bus (referred to as the CPU local bus) which interconnects the CPU, cache memory and cache control. Other devices are coupled to a different bus (system bus). Such other devices include for example main memory, I/O devices and ancillary apparatus. In addition to the foregoing devices, the system bus may also be coupled to the cache control.
The cache subsystem typically relieves the system bus from a large proportion of memory accesses that would otherwise be carried by the system bus in the absence of the cache subsystem. That is, to the extent that the CPU can obtain information from the cache memory, then for that particular cycle the CPU does not require access to the system bus. Accordingly, other devices can, during the same period of time, use the system bus for other operations. This is expected to result in a significant reduction of the system bus cycles which are actually used by the CPU. Usually the cache control is coupled to both the system bus and the CPU local bus, and one of the functions of the cache control is to supervise the arbitration supervisor which, in the single bus systems, had been supervised by the CPU.
One available cache controller, the 82385, has the capability of operating in a master or a slave mode. When the 82385 is operated in the master mode, and supervises the arbitration supervisor, there is no longer any mechanism for the CPU to contend for the system bus resource.
Accordingly, it is an object of this invention to provide a mechanism whereby a CPU, in a multi-bus microcomputer system with a cache control element supervising the arbitration supervisor, may access the system bus resource distributed by the arbitration mechanism.
The arbitration supervisor as described in the above-referenced applications, responds to arbitration request signals which are coupled in common from a plurality of devices. When the arbitration supervisor recognizes that one or more devices has requested the common resource, it signals the beginning of an arbitration period by changing the condition of a conductor (the ARB/GRANT is accessible to all the contending devices). When the contending devices see the condition of this conductor changed so as to signal the beginning of an arbitration period, the devices generate signals corresponding to their priority levels and drive a plurality of arbitration conductors dedicated to this function with those signals. The connection between the plurality of devices and the arbitration conductors are arranged such that the conductors assume that priority value of the highest priority circuit driving the arbitration conductors. Each device can therefore recognize, by comparing the priority value on the arbitration conductors with its own priority value, whether there is any higher priority device contending for access to the bus. At the termination of a predetermined arbitration period, the ARB/GRANT conductor changes state. This begins the grant period, during which that contending device whose priority value was the priority value on the arbitration conductors assumes control of the common resource to initiate a bus cycle.
Furthermore, as described in the above-referenced applications, there is still another conductor dedicated to a PREEMPT signal which can be generated to force a device having received access to the system resource, to terminate its access. Thus, a device which has received access to the system resource and is using that resource, on recognizing an asserted preempt, is required to initiate an orderly termination of its use of the system resource. When the device which is thus preempted terminates its use of the common resource, the arbitration supervisor begins a new arbitration period as described above.
In microcomputer systems with a cache subsystem, the CPU cycles accessing cache (and thus not requiring access to the system bus) are cycles of minimum duration or zero wait state cycles. When CPU cycles extend beyond this minimum, they signal CPU requirements for the system bus. Thus CPU cycles of longer than the minimum duration signal CPU need for the system bus, the common resource.
In accordance with the invention, the CPU is provided with the means to generate a PREEMPT signal which will cause any device having gained access to the bus through the arbitration mechanism to terminate that access as has already been described. As will be described, the CPU's generation of PREEMPT is controlled by detecting a CPU cycle of duration longer than one required for a cache address.
However, the CPU's use of the system resource is arranged to conserve as much time as possible. More particularly, when a device which had gained access to the bus via an arbitration recognizes a preempt and initiates an orderly termination of its bus access, it signals its termination of the use of the bus. The arbitration supervisor responds to this indication by generating a new arbitration period. If the CPU was the device which had generated the preempt to require release of the bus, it will respond differently to the beginning of the arbitration period than will any other device contending for bus access. At the beginning of the arbitration period, each of the other devices contending for access to the bus places its priority value on the arbitration conductors. The CPU does not enter into this process at all; with the beginning of the arbitration period, the CPU actually begins using the bus.
In an embodiment of the invention which has actually been constructed, the minimum arbitration period is 300 nanoseconds. However a zero wait state bus cycle is less than 300 nanoseconds. Accordingly, whenever the CPU preempts and thereby gains access to the system bus, it can actually complete a cycle simultaneously with the arbitration process.
Accordingly, the present invention provides the CPU with means to preempt use of the system bus which had previously been distributed based on an arbitration mechanism. Furthermore, in accordance with the present invention, when the CPU obtains access to the system bus via its preempt signal, it can initiate a bus cycle which can be completed during the duration that other devices contend for access to the bus.
Thus in one aspect, the invention provides a multi-bus microcomputer system comprising:
a) a processor and a cache subsystem connected together by a CPU local bus,
b) a random access memory, an arbitration supervisor and a plurality of other functional units connected together by a system bus,
c) means coupling said CPU local bus and said system bus,
d) where both said CPU local bus and said system bus include a plurality of conductors dedicated to arbitrating access to said system bus by at least some of said plurality of other functional units, one of said plurality of said conductors providing a preempt signal, and
e) a preempt signal source with inputs responsive to a CPU local bus cycle extending beyond a minimum duration, said preempt signal source having an output coupled to said CPU local bus for generating a preempt signal effective at any functional unit with access to said system bus for limiting a duration of said access in response to receipt of said preempt signal.